This invention relates to integrated circuits, and more particularly, to integrated circuits that include memory. Integrated circuits often contain memory elements such as random-access memory cells for storing data.
On programmable integrated circuits, memory elements can be used to store configuration data. Once loaded with a configuration data bit, a memory element can supply a static control signal to the gate of a programmable logic transistor (often referred to as a pass transistor). The logic high or logic low state of the configuration bit determines whether the pass transistor is turned on or off. By configuring numerous pass transistors, programmable logic on a programmable integrated circuit can be configured to perform a custom logic function.
Pass transistors that receive the static control signals from the memory elements are typically formed from n-channel transistors. When a low voltage is applied to the gate of an n-channel pass gate, the pass gate will be turned off and signals will be prevented from passing between its source-drain terminals. When a high voltage is applied to the gate of an n-channel pass gate, signals are allowed to pass between its source-drain terminals.
Due to the electrical properties of n-channel metal-oxide-semiconductor transistors, it is difficult to pass a logic one value between the source-drain terminals of an n-channel pass transistor if the controlling voltage that is applied to the gate of the pass transistor has the same magnitude as the logic one value. As a result, programmable integrated circuits are sometimes provided with memory elements that supply static control signals at elevated voltage levels. These elevated control signals overdrive the pass transistors when the pass transistors are turned on thereby improving its drive strength.
The memory elements that supply the elevated control signals are biased using an elevated positive power supply voltage (i.e., a positive power supply voltage greater than the nominal positive power supply voltage that is used to power the remaining logic circuits on the programmable integrated circuit). Biasing memory elements in this way may, however, result in increased leakage and power consumption. For example, a memory element may include first and second cross-coupled inverters each having an n-channel transistor coupled in series with a p-channel transistor. When the memory element is storing a given data bit, the n-channel transistor in the first inverter may be turned on while the n-channel transistor in the second inverter may be turned off. The n-channel transistor that is turned off will have a drain terminal that receives the elevated positive power supply voltage and a gate terminal, source terminal, and body (bulk) terminal that receives a ground voltage. An n-channel transistor biased as such may experience substantial leakage current flowing from its drain terminal into its body terminal due to gate-induced drain leakage effects, band-to-band tunneling, avalanche breakdown, and other sub-threshold leakage effects.
In an effort to mitigate this type of leakage, techniques have been developed that involve reverse biasing the body terminals of the n-channel transistors in the memory elements (i.e., by supplying the body terminals with a negative voltage). Biasing the body terminal using negative voltages to increase the reverse bias between the source and body terminals will serve to increase the transistor threshold voltage, thereby reducing sub-threshold leakage.
If, however, the bulk of the n-channel transistor is formed near an actively driven gate structure of an adjacent transistor (i.e., where the gate structure of the adjacent transistor is biased to some positive voltage level), the voltage difference between that gate structure and the bulk of the n-channel transistor will generate an unacceptable amount of leakage current (due to hot carrier injection mechanisms). This effect is exacerbated in modern integrated circuit fabrication processes in which transistors are formed closer to one another. As a result, leakage current flowing from a positively driven gate terminal of one transistor to a reverse biased bulk terminal of a closely formed neighboring transistor may negate any leakage improvement achieved using conventional reverse biasing techniques.